1. Field of the Invention
This invention relates to high performance densely packed bipolar transistors with minimum spacing and a fabrication process therefor using one masking step for self-aligning the device with the isolation area and employing molecular-beam-epitaxy crystal growth techniques.
2. Background Art
U.S. Pat. No. 4,428,111, issued Jan. 31, 1984 to Swartz, entitled MICROWAVE TRANSISTOR, is of interest because it relates to a method using molecular-beam-epitaxy. In the patent, a process for fabricating a high speed bipolar transistor is described wherein the collector, base and emitter layers are first grown using molecular-beam-epitaxy (MBE). A mesa etch is performed to isolate a base-emitter region, and a contact layer is grown using MBE over this isolated region to make contact with the thin base layer. The contact layer is selectively etched to expose the emitter layer, and metal is deposited to fabricate emitter, base and collector contacts.
In U.S. Pat. No. 4,571,817, issued Feb. 25, 1986 to Birritella et al, entitled "METHOD OF MAKING CLOSELY SPACED CONTACTS TO PN-JUNCTION USING STACKED POLYSILICON LAYERS, DIFFERENTIAL ETCHING AND ION IMPLANTATIONS", a means and method is described for forming closely spaced contacts to adjacent semiconductor regions, such as the base and emitter of a bipolar transistor, so that the lateral voltage drops between the contacts and an intervening junction are minimized. The emitter and base and the contacts thereto are self-aligned. This is accomplished by a structure utilizing two poly-layers separated by one or more intermediate dielectric layers. The upper of the two poly-layers serves as a selective etching mask for defining the contact geometry and separation. The lower of the two poly-layers has one portion which becomes a poly-contact and diffusion source for the base region and a second portion which becomes a poly-contact and diffusion source for the emitter region. A single mask is used in connection with ion bombardment to alter the etch rate of portions of the poly-layers. This mask together with subsequent etch steps defines the emitter width and location and the base-emitter contact separation. The process is self-aligning.
The following references are of interest because they show a sidewall method during bipolar manufacture.
U.S. Pat. No. 4,586,968, issued May 6, 1986 to Coello-Vera, entitled PROCESS OF MANUFACTURING A HIGH FREQUENCY BIPOLAR TRANSISTOR UTILIZING DOPED SILICIDE WITH SELF-ALIGNED MASKING discloses a transistor which includes base fingers, a titanium silicide coating, from which the base diffusions have been formed, and a silicon nitride coating.
The edges of sandwiches made up of bands are bordered by a silica bank formed automatically by deposit and anisotropic attack, without additional masking. Emitter fingers are overhung by a polycrystalline silicon layer from which doping of these fingers has been obtained.
The possibility is also obtained, automatically and without masks alignment, of having the emitter and base fingers brought firmly together with minimum protection distances.
FR No. 2549-293-A, dated Jan. 18, 1985, describes a transistor that consists of a semiconductor wafer with zones of alternate conduction type forming fingers in its surface for the emitter and base. The base finger forms a sandwich with at least a first conducting strip consisting of a metal/silicon compound (esp. titantium silicide) and a second insulating strip. Insulating banks support the side walls of the sandwich and extend far enough to cover the extremities of the base and emitter fingers.
The emitter fingers are covered by at least one conducting layer extending over the two adjacent insulating strips
U.S. Defensive Publication No. T104,102, dated Apr. 3. 1984, to Ho et al, entitled POLYSILICON-BASE SELF-ALIGNED BIPOLAR TRANSISTOR PROCESS AND STRUCTURE describes a bipolar transistor isolated by deep recessed oxide with shallow recessed oxide separating the base from collector contact with polysilicon contact to base extrinsic region, the polysilicon being self-aligned with the emitter and the emitter contact.
U.S. Pat. No. 4,521,952, issued June 11, 1985 to Riseman, entitled METHOD OF MAKING INTEGRATED CIRCUITS USING METAL SILICIDE CONTACTS discloses a metal silicide contact to silicon devices which has broad application to almost all of the variety of silicon semiconductor devices is described. This contact with a substantial side component has particular advantage as the base contact for a bipolar transistor.
The publication by Shepard entitled SELF-ALIGNED BIPOLAR TRANSISTOR, IBM Technical Disclosure Bulletin, Vol. 27, No. 2, July 1984, pp. 1008-1009, also describes a bipolar transistor side wall structure.
The following references are typical of the present state of the transistor process art.
U.S. Pat. No. 4,508,579, issued Apr. 2, 1985 to Goth et al, entitled LATERAL DEVICE STRUCTURES USING SELF-ALIGNED FABRICATION TECHNIQUES.
U.S. Pat. No. 4,572,765, issued Feb. 25, 1986 to Berry, entitled METHOD OF FABRICATING INTEGRATED CIRCUIT STRUCTURES USING REPLICA PATTERNING.
U.S. Pat. No. 4,433,470, issued Feb. 28, 1984 to Kameyama et al, entitled METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE UTILIZING SELECTIVE ETCHING AND DIFFUSION.
U.S. Pat. No. 4,252,582, issued Feb. 24, 1981 to Anantha et al, entitled SELF ALIGNED METHOD FOR MAKING BIPOLAR TRANSISTOR HAVING MINIMUM BASE TO EMITTER CONTACT SPACING.
U.S. Pat. No. 4,378,630, issued Apr. 5, 1983 to Horng et al, entitled PROCESS FOR FABRICATING A HIGH PERFORMANCE PNP AND NPN STRUCTURE.
U.S. Pat. No. 4,392,149, issued July 5, 1983 to Horng et al, entitled BIPOLAR TRANSISTOR.